A memory cell incorporated in a nonvolatile memory device typified by a resistance change memory is an element capable of electrically switching at least two resistance values (for example, a high resistance state and a low resistance state). The memory cell (bit) is located at the intersection of an upper wiring (bit line) and a lower wiring (word line). Memory cells are arranged two-dimensionally to form a memory cell array. A memory cell array of a multiple-layer structure is formed by stacking memory cell arrays.
When performing an operation in which a selected bit, which is a selected memory cell, is rewritten from the low resistance state to the high resistance state (reset operation) or an operation in which the bit is rewritten from the high resistance state to the low resistance state (set operation), a voltage is applied between the bit line and the word line connected to the selected memory cell. That is, voltage pulse is applied to the selected memory cell in the set/reset operation. Normally the resistance value is switched by one pulse application.
However, when the cycle of changing the resistance value is repeated many times, there may be a case where the resistance value does not change even when a voltage pulse is applied multiple times. This selected bit is referred to as a faulty bit in the following. It is a waste of time to apply a voltage pulse to the faulty bit multiple times to attempt the set/reset operation, and this may lead to a performance reduction of the resistance change memory.